 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| aSC7611 HARDWARE MONITOR WITH INTEGRATED FAN CONTROL Preliminary Specification Product Description The aSC7611 has a two wire digital interface compatible with SMBus 2.0. Using a 10-bit - ADC, the aSC7611 measures the temperature of two remote diode connected transistors as well as its own die. Using temperature information from these three zones, an automatic fan speed control algorithm is employed to minimize acoustic impact while achieving recommended CPU temperature under varying operational loads. To set fan speed, the aSC7611 has three independent pulse width modulation (PWM) outputs that are controlled by one, or a combination of three, temperature zones. Both high- and low-frequency PWM ranges are supported. The aSC7611 also includes a digital filter that can be invoked to smooth temperature readings for better control of fan speed and minimum acoustic impact. The aSC7611 has tachometer inputs to measure fan speed on up to four fans. Limit and status registers for all measured values are included to alert the system host that any measurements are outside of programmed limits via status registers. System voltages of VCCP, 2.5V, 3.3V, 5.0V, and 12V motherboard power are monitored efficiently with internal scaling resistors. PRODUCT SPECIFICATION Measurement System Temperature: * 0.25C resolution, 2C accuracy on remote diode * 0.25C resolution, 3C accuracy on local sensor * Temperature measurement range on remote sensor -55C to +125C using 2's complement coding. Voltage: * 10-bit Resolution, 2% of Full Scale Fan Tachometer: * 16-bit count of 90kHz clock periods Limit alarms for all measured values Preliminary Specification - Subject to change without notice Preliminary Specification - Subject to change without notice Applications * * * Desktop Computers - Motherboards and Graphics Cards Laptop Computers Microprocessor based equipment (e.g. Basestations, Routers, ATMs, Point of Sales) Features * * * * * * * * * * * * * 2-wire, SMBus 2.0 compliant, serial interface 10-bit -ADC Monitors internal and remote thermal diodes Monitors VCCP, 2.5V, 3.3V, 5.0V, and 12V motherboard/processor supplies Programmable autonomous fan control based on temperature readings Noise filtering of temperature reading for fan control 0.25C digital temperature sensor resolution 3 PWM fan speed control outputs for 2-, 3- or 4wire fans. Provides high and low PWM frequency ranges 4 fan tachometer inputs Monitors 5 VID control lines 24-Lead QSOP package XOR-tree test mode Connection Diagram SMBDAT SMBCLK GND 3.3V VID0 VID1 VID2 VID3 TACH3 PWM2 TACH1 TACH2 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 PWM1/ XTESTOUT VCCP 2.5V 12V 5V VID4 REMOTE 1+ REMOTE 1REMOTE 2+ REMOTE 2TACH4/ AddressSelect PWM3/ AddressEnable aSC7611 19 18 17 16 15 14 13 Ordering Information Part Number ASC7611QS24 Package 24-lead QSOP Temperature Range and Operating Voltage 0C to +120C, 3.3V Marking aSC7611 Ayww How Supplied 2500 units Tape & Reel Ayww - Assembly site, year, workweek (c) Andigilog, Inc. 2006 -1www.andigilog.com October 2006 - 70A05007 aSC7611 Block Diagram SERIAL BUS INTERFACE VID0 VID1 VID2 VID3 SMBDAT SMBCLK VID 0-4 REGISTER VOLTAGE FAN SPEED TEMPERATURE, AND LIMIT VALUE REGISTERS Preliminary Specification - Subject to change without notice TACH1 TACH2 TACH3 TACH4/ Address Select 3.3V 5V 12V 2.5V VCCP REMOTE 1+ REMOTE 1REMOTE 2REMOTE 2+ FAN SPEED COUNTER STEPPING AND DEVICE ID REGISTERS LIMIT COMPARATORS Preliminary Specification - Subject to change without notice STATUS REGISTERS ADDRESS POINTER REGISTERS CONFIGURATION REGISTERS SPIKE SMOOTHING FAN TMIN/TRANGE/ HYST REGISTERS FAN CHARACTERISTICS FAN SPEED CONFIG REGISTERS FAN PWM CONTROL & PWM VALUE REGISTERS PWM3/ AddressEnable PWM2 INPUT ATTENUATORS, EXTERNAL DIODE SIGNAL CONDITIONING, AND ANALOG MULTIPLEXER PWM1 10-bit -ADC INTERNAL TEMP SENSOR BANDGAP REFERENCE Figure 1 Block Diagram (c) Andigilog, Inc. 2006 -2www.andigilog.com October 2006 - 70A05007 aSC7611 Pin Descriptions Symbol SMBus SMBDAT SMBCLK VID0 Processor VID Lines VID1 VID2 VID3 VID4 3.3V Power Pin 1 2 5 6 7 8 19 4 Type Digital I/O (Open-Drain) Digital Input Digital Input Digital Input Digital Input Digital Input Digital Input POWER Name and Function/Connection System Management Bus Data. Open-drain output. 5V tolerant, SMBus 2.0 compliant. System Management Bus Clock. Tied to Open-drain output. 5V tolerant, SMBus 2.0 compliant. Voltage identification signal from the processor. This value is read in VID0-VID4 Status Register. Voltage identification signal from the processor. This value is read in VID0-VID4 Status Register. Voltage identification signal from the processor. This value is read in VID0-VID4 Status Register. Voltage identification signal from the processor. This value is read in VID0-VID4 Status Register. Voltage identification signal from the processor. This value is read in VID0-VID4 Status Register. +3.3V pin. Can be powered by +3.3V Standby power if monitoring in low power states is required. This pin should be bypassed with a 0.1F capacitor in parallel with 100pF. A bulk capacitance of approximately 10F needs to be in near vicinity of the aSC7611. Ground for all analog and digital circuitry. Analog Input for +5V monitoring. Analog Input for +12V monitoring. Analog Input for +2.5V monitoring.. Analog Input for VCCP (processor voltage) monitoring. Positive input (current source) from the first remote thermal diode Serves as the positive input into the A/D. Connected to THERMDA pin of Pentium processor. Negative input (current sink) from the first remote thermal diode Serves as the negative input into the A/D. Connected to THERMDC pin of Pentium processor. Positive input (current source) from the first remote thermal diode Serves as the positive input into the A/D. Connected to the base of a diode connected MMBT3904 NPN transistor. Negative input (current sink) from the first remote thermal diode Serves as the negative input into the A/D. Connected to the emitter of a diode connected MMBT3904 NPN transistor. Input for monitoring tachometer output of fan 1. Input for monitoring tachometer output of fan 2. Input for monitoring tachometer output of fan 3. During power-up, if held low through a 10K resistor, SMBus address may be selected based on the state of TACH4 pin. Input for monitoring tachometer output of fan 4. If in Address Select Mode, determines the SMBus address of aSC7611. Preliminary Specification - Subject to change without notice Preliminary Specification - Subject to change without notice GND 5V Voltage Inputs 12V 2.5V VCCP Remote 1+ 3 20 21 22 23 18 GROUND Analog Input Analog Input Analog Input Analog Input Remote Thermal Diode Positive Input Remote Thermal Diode Negative Input Remote Thermal Diode Positive Output Remote Thermal Diode Negative Input Digital Input Digital Input Digital Input Remote 1Remote 17 Remote 2+ 16 Remote 2- 15 TACH1 Fan Tachometer Inputs TACH2 TACH3/AddressEnable 11 12 9 14 TACH4/AddressSelect Digital Input (c) Andigilog, Inc. 2006 -3www.andigilog.com October 2006 - 70A05007 aSC7611 Symbol PWM1/XTESTOUT Fan Control PWM2 Pin 24 10 13 PWM3/Address Enable Type Digital OpenDrain Output Digital OpenDrain Output Digital OpenDrain Output Name and Function/Connection Fan speed control 1. When in XOR tree test mode, functions as XOR Tree output. Fan speed control 2. Fan speed control 3. Pull to ground at power on to enable Address Select Mode (Address Select pin controls SMBus address of the device). Absolute Maximum Ratings1 Parameter Supply Voltage, VDD Voltage on Any Digital Input or Output Pin Rating -0.5V to 6.0V -0.5V to 6.0V -0.5V to 16V -0.5V to 6.6V -0.5V to (VDD + 0.50V) -0.5V to 6.0V 1mA 5mA 20mA See (Note 3) -65C to +150C 3000 V 200 V 1500 V Operating Ratings1 Parameter aSC7611 Operating Temperature Range, Ambient Temperature, TMIN to TMAX Remote Diode Temperature Range Supply Voltage (3.3V nominal) VIN Voltage Range +12V VIN +5V VIN +3.3V VIN VCCP and All Other Inputs VID0-VID4 All Other Inputs Typical Supply Current -0.05V to 16V -0.05V to 6.6V 3.0V to 4.4V -0.05V to VDD + 0.05V -0.05V to 5.5V -0.05V to VDD + 0.05V 1.8mA Rating 0C TA +120C Preliminary Specification - Subject to change without notice Preliminary Specification - Subject to change without notice Voltage on 12V Analog Input Voltage on 5V Analog Input Voltage on Remote 1 +, Remote 2 + Voltage on Other Analog Inputs Current on Remote 1 -, Remote 2 Input Current on Any Pin2 Package Input Current Storage Temperature Human Body Model ESD4 Machine Model Charged Device Model Notes: 2 -55C TD +125C +3.0V to +3.6V Package Dissipation at TA = 25C 1. Absolute maximum ratings are limits beyond which operation may cause permanent damage to the device. These are stress ratings only; functional operation at or above these limits is not implied. 2. When the input voltage (VIN) at any pin exceeds the power supplies (VIN < GND or VIN > VDD), the current at that pin should be limited to 5mA. The 20mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5mA to four. Parasitic components and/or ESD protection circuitry are present on the aSC7611 pins. Care should be taken not to forward bias the parasitic diode present on pins D+ and D-. Doing so by more than 50mV may corrupt temperature measurements. 3. Thermal resistance junction-to-ambient when attached to a double-sided printed circuit board with 1oz. foil is 115C/W 4. Human Body Model: 100pF capacitor discharged through a 1.5k resistor into each pin. Machine Model: 200pF capacitor discharged directly into each pin. Charged-Device Model is per JESD22-C101C. (c) Andigilog, Inc. 2006 -4www.andigilog.com October 2006 - 70A05007 aSC7611 DC Electrical Characteristics5 The following specifications apply for VDD = 3.0V to 3.6V, and all analog input source impedance Rs = 50 unless otherwise specified in conditions. Boldface limits apply for TA = TJ over TMIN to TMAX; all other limits TA = TJ = 25C. TA is the ambient temperature of the aSC7611; TJ is the junction temperature of aSC7611; TD is the remote thermal diode junction temperature. Specifications subject to change without notice Parameter POWER SUPPLY CHARACTERISTICS Supply Current Converting, Interface and Fans Inactive, Peak Current Converting, Interface and Fans inactive, Average Current 1.6 1.8 0.5 2.8 3.5 mA(max) mA V Conditions Min Typ Max Units Preliminary Specification - Subject to change without notice Preliminary Specification - Subject to change without notice Power-On Reset Threshold Voltage TEMPERATURE TO DIGITAL CONVERTER CHARACTERISTICS Resolution 0C T A +100C, 0CTD +100C, 3VVDD3.6V 0C T A +120C, -55CTD +125C, 3VVDD3.6V 0C T A +120C, 3V V D D 3.6V IDS High Level Low Level 0.25 10 2 C Bits C Remote Sensor Accuracy 6 3 1 96 6 16 3 C C A(max) A Temperature Accuracy using 7 Internal Diode External Diode Current Source External Diode Current Ratio ANALOG TO DIGITAL CONVERTER CHARACTERISTICS Total Unadjusted Error8 Differential Non-linearity Power Supply Sensitivity Total Monitoring Cycle Time9 Input Resistance, all analog inputs DIGITAL OUTPUT: PWM1, PWM2, PWM3, XTESTOUT Logic Low Sink Current Logic Low Level Logic Low Output Voltage High Level Output Current Logic Input High Voltage Logic Input Low Voltage Logic Input Hysteresis Voltage DIGITAL INPUTS: ALL Logic Input High Voltage (c) Andigilog, Inc. 2006 TUE DNL All Voltage and Temperature readings 140 1 1 182 210 2 %FS(max) LSB %/V 200 400 ms (max) k IOL VOL VOL IOH VIH VIL VHYST VIH VOL = 0.4V IOUT = +8mA IOUT = +4mA VOUT = V+ 8 0.4 0.4 0.1 2.1 0.8 300 2.1 10 mA (min) V (max) V (max) A(max) V (min) V (max) mV V (min) October 2006 - 70A05007 SMBUS OPEN-DRAIN OUTPUT: SMBDAT SMBUS INPUTS: SMBCLK, SMBDAT -5www.andigilog.com aSC7611 Parameter Logic Input Low Voltage Logic Input Threshold Voltage Logic High Input Current Logic Low Input Current Digital Input Capacitance VIL VTH IIH IIL CIN VIN = V+ VIN = GND 1.5 0.005 -0.005 20 10 -10 Conditions Min Typ Max 0.8 Units V (max) V A(max) A(max) pF AC Electrical Characteristics The following specifications apply for VDD = 3.0V to 3.6V unless otherwise specified in conditions. Boldface limits apply for TA = TJ over TMIN to TMAX; all other limits TA = TJ = 25C. Parameter TACHOMETER Conditions Min Typ Max Units Preliminary Specification - Subject to change without notice Preliminary Specification - Subject to change without notice Fan Full-Scale Count Fan Counter Clock Frequency Fan Count Conversion Time FAN PWM OUTPUT Low-Frequency Range Frequency Range High-Frequency Range Duty-Cycle Range Duty-Cycle Resolution (8-bits) Spin-Up Time Interval Range 0.3906 0 4000 10 94 23 30 90 0.7 65535 1.46 (max) kHz sec(max) Hz Hz kHz kHz 0 to 100 %(max) %/count ms ms Logic Electrical Characteristics (TA = 25 C, VDD = 3.3V unless otherwise noted) Parameter Input Voltage Logic High Input Voltage Logic Low Input Leakage Current SMBus Output Sink Current SMBus Logic Input Current Output Leakage Current Output Transition Time Input Capacitance Symbol VIH VIL IIN IOL IIH, IIL IOH tF CIN VOH = VDD = 5.5V CL= 400pF, IOL = -3mA All Digital Inputs Conditions 3V V D D 3.6V 3V V D D 3.6V VIN = 0V or 5.5V, 0C T A +125C TA = 25 C, VOL = 0.6V 6 -1 0.1 +1 1 250 5 Min 2.1 0.8 1.0 Typ Max Units V V A mA A A ns pF (c) Andigilog, Inc. 2006 -6www.andigilog.com October 2006 - 70A05007 aSC7611 Serial Port Timing (TA = 25 C, VDD = 3.3V unless otherwise noted, Guaranteed by design, not production tested) Parameter SCL Operating Frequency SCL Clock Transition Time SCL Clock Low Period SCL Clock High Period Bus free time between a Stop and a new Start Condition Data in Set-Up to SCL High Data Out Stable after SCL Low SCL Low Set-up to SDA Low (Repeated Start Condition) SCL High Hold after SDA Low (Start Condition) Symbol fSCL tT:LH , tT:HL tLOW tHIGH tBUF tSU:DAT tHD:DAT tSU:STA tHD:STA tSU:STO tPOR tTIMEOUT 25 1.3 0.6 1.3 100 300 600 600 600 500 35 50 Min Typ Max 400 300 Units kHz ns s s s ns ns ns ns ns ms ms Preliminary Specification - Subject to change without notice Preliminary Specification - Subject to change without notice SDA High after SCL High (Stop Condition) Time in which aSC7611 must be operational after a power-on reset SMBus Time-out before device communication interface reset10 SCL tHD:STA tSU:DAT tSU:STA tSU:STO SDA tBUF tLOW tHIGH tT:LH 90 10 tT:HL 90 10 SCL SDA Data Out Notes (cont'd): tHD:DAT 5. These specifications are guaranteed only for the test conditions listed. 6. The accuracy of the aSC7611 is guaranteed when using the thermal diode of Intel Pentium 4, 65nm processors or any thermal diode with a non-ideality of 1.009 and series resistance of 4.52. When using a 2N3904 type transistor or an CPU with a different non-ideality the error band will be typically shifted depending on transistor diode or CPU characteristics. See applications section for details. 7. Accuracy (expressed in C) = Difference between the aSC7611 reported output temperature and the temperature being measured. Local temperature accuracy does not include the effects of self-heating. The rise in temperature due to self-heating is the product of the internal power dissipation of the aSC7611 and the thermal resistance. See (Note 3) for the thermal resistance to be used in the self-heating calculation. 8. TUE, total unadjusted error, includes ADC gain, offset, linearity and reference errors. TUE is defined as the "actual Vin" to achieve a given code transition minus the "theoretical Vin " for the same code. Therefore, a positive error indicates that the input voltage is greater than the theoretical input voltage for a given code. If the theoretical input voltage was applied to an aSC7611 that has positive error, the aSC7611's reading would be less than the theoretical. 9. This specification is provided only to indicate how often temperature and voltage data is updated. The aSC7611 can be read at any time without regard to conversion state (and will yield last conversion result). 10. Holding the SMBCLK lines low for a time interval greater than tTIMEOUT will reset the aSC7611's SMBus state machine, therefore setting the SMBDAT pin to a high impedance state. (c) Andigilog, Inc. 2006 -7www.andigilog.com October 2006 - 70A05007 aSC7611 Control Communication SMBus The aSC7611 is compatible with devices that are compliant to the SMBus 2.0 specifications. More information on this bus can be found at http://www.smbus.org/. Compatibility of SMBus2.0 to other buses is discussed in the SMBus 2.0 specification. Slave Address aSC7611 is designed to be used primarily in desktop systems that require only one monitoring device. If only one aSC7611 is used on the motherboard, the designer should be sure that the AddressEnable /PWM3 pin is High during the first SMBus communication addressing the aSC7611. AddressEnable /PWM3 is an open drain I/O pin that at General Operation Writing to and reading from the aSC7611 registers is accomplished via the SMBus-compatible two-wire serial interface. SMBus protocol requires that one device on the bus initiate and control all read and write operations. This device is called the "master" device. The master device also generates the SCL signal that is the clock signal for all other devices on the bus. All other devices on the bus are called "slave" devices. The aSC7611 is a slave device. Both the master and slave devices can send and receive data on the bus. During SMBus operations, one data bit is transmitted per clock cycle. All SMBus operations follow a repeating nine clock-cycle pattern that consists of eight bits (one byte) of transmitted data followed by an acknowledge (ACK) or not acknowledge (NACK) from the receiving device. Note that there are no unused clock cycles during any operation-- therefore there must be no breaks in the stream of data and ACKs / NACKs during data transfers. For most operations, SMBus protocol requires the SDA line to remain stable (unmoving) whenever SCL is high -- i.e. any transitions on the SDA line can only occur when SCL is low. The exceptions to this rule are when the master device issues a start or stop condition. Note that the slave device cannot issue a start or stop condition. power-on defaults to the input state of AddressEnable . A maximum of 10k pull-up resistance on AddressEnable /PWM3 is required to assure that the SMBus address of the device will be locked at 010 1110b, which is the default address of the aSC7611. Preliminary Specification - Subject to change without notice Preliminary Specification - Subject to change without notice During the first SMBus communication TACH4 and PWM3 can be used to change the SMBus address of the aSC7611 to 0101101b or 0101100b. aSC7611 address selection procedure: A 10k pull-down resistor to ground on the AddressEnable /PWM3 pin is required. Upon power up, the aSC7611 will be placed into AddressEnable mode and assign itself on SMBus address according to the state of the Address Select input. The aSC7611 will latch the address during the first valid SMBus transaction in which the first five bits of the targeted address match those of the aSC7611 address, 0 1011b. This feature eliminates the possibility of a glitch on the SMBus interfering with address selection. When the AddressEnable /PWM3 pin is not used to change the SMBus address of the aSC7611, it will remain in a high state until the first communication with the aSC7611. After the first SMBus transaction is completed PWM3 and TACH4 will return to normal operation. Address Select Board Implementation Both pins pulled to ground through a 10 k resistor Address Select pulled to 3.3V and AddressEnable pulled to GND through a 10 k resistor AddressEnable pulled to 3.3V through a 10 k resistor SMBus Definitions The following are definitions for some general SMBus terms: Start Condition: This condition occurs when the SDA line transitions from high to low while SCL is high. The master device uses this condition to indicate that a data transfer is about to begin. Stop Condition: This condition occurs when the SDA line transitions from low to high while SCL is high. The master device uses this condition to signal the end of a data transfer. Acknowledge and Not Acknowledge: When data are transferred to the slave device it sends an "acknowledge" (ACK) after receiving each byte. The receiving device sends an ACK by pulling SDA low for one clock. Following the last byte, a master device sends a "not acknowledge" (NACK) followed by a stop condition. A NACK is indicated by forcing SDA high during the clock after the last byte. Address Enable 0 SMBus Address Binary 010 1100 Hex 2Ch 0 0 1 010 1101 2Dh 1 X 010 1110 2Eh (c) Andigilog, Inc. 2006 -8www.andigilog.com October 2006 - 70A05007 aSC7611 In this way, up to three aSC7611 devices can exists on a SMBus at any time. Multiple aSC7611 devices can be used to monitor additional processors in the temperature zones. When using the non-default addresses, additional circuitry will be required if Tach4 and PWM3 require to function correctly. Such circuitry could consist of GPIO pins from a micro-controller. During the first communication the micro-controller would drive the AddressEnable and Address Select pins to the proper state for the required address. After the first SMBus communication the micro-controller would drive its pins into Tri-State allowing TACH4 and PWM3 to operate correctly. Writing to Registers All writes must start with a pointer set as described previously, even if the pointer is already pointing to the desired register. The sequence is described in Figure 2. Immediately following the pointer set, the master must begin transmitting the data to be written. After transmitting each byte of data, the master must release the SDA line for one clock to allow the aSC7611 to acknowledge receiving the byte. The write operation should be terminated by a stop condition from the master. Reading from Registers Preliminary Specification - Subject to change without notice Writing to and Reading from the aSC7611 All read and write operations must begin with a start condition generated by the master device. After the start condition, the master device must immediately send a slave address (7-bits) followed by a R/ W bit. If the slave address matches the address of the aSC7611, it sends an ACK by pulling the SDA line low for one clock. Read or write operations may contain one- or two-bytes. See Figures 2 through 6 for timing diagrams for all aSC7611 operations. To read from a register other than the one currently being pointed to by the address pointer register, a pointer set sequence to the desired register must be done as described previously. Immediately following the pointer set, the master must perform a repeat start condition that indicates to the aSC7611 that a read is about to occur. It is important to note that if the repeat start condition does not occur, the aSC7611 will assume that a write is taking place, and the selected register will be overwritten by the upcoming data on the data bus. The read sequence is described in Figure 4. After the start condition, the master must again send the device address and read/write bit. This time the R/ W bit must be set to 1 to indicate a read. The rest of the read cycle is the same as described in the previous paragraph for reading from a preset pointer location. If the pointer is already pointing to the desired register, the master can read from that register by setting the R/ W bit (following the slave address) to a 1. After sending an ACK, the aSC7611 will begin transmitting data during the following clock cycle. After receiving the 8 data bits, the master device should respond with a NACK followed by a stop condition. If the master is reset while the aSC7611 is in the process of being read, the master should perform an SMBus reset. This is done by holding the data or clock low for more than 35ms, allowing all SMBus devices to be reset. This follows the SMBus 2.0 specification of 25-35ms. When the aSC7611 detects an SMBus reset, it will prepare to accept a new start sequence and resume communication from a known state. Preliminary Specification - Subject to change without notice Setting the Register Address Pointer For all operations, the address pointer stored in the address pointer register must be pointing to the register address that is going to be written to or read from. This register's content is automatically set to the value of the first byte following the R/ W bit being set to 0. After the aSC7611 sends an ACK in response to receiving the address and R/ W bit, the master device must transmit an appropriate 8-bit address pointer value as explained in the Registers section of this data sheet. The aSC7611 will send an ACK after receiving the new pointer data. The register address pointer set operation is illustrated in Figure 2. If the address pointer is not a valid address the aSC7611 will internally terminate the operation. Also recall that the address register retains the current address pointer value between operations. Therefore, once a register is being pointed to, subsequent read operations do not require another Address Pointer set cycle. (c) Andigilog, Inc. 2006 -9www.andigilog.com October 2006 - 70A05007 aSC7611 Note: The following figures assume that Device Address 2Ch has been chosen by the user. 1 SCL SDA S 0 1 0 1 1 0 0 R/W A A7 A6 A5 A4 A3 A2 A1 A0 A 9 1 9 Start SMBus Device Address Byte (2Ch) ACK from aSC7611 Register Address Byte ACK from aSC7611 Stop By Master Figure 2 Register Address Pointer Set 1 SCL 9 1 9 1 9 Preliminary Specification - Subject to change without notice Preliminary Specification - Subject to change without notice SDA S 0 1 0 1 1 0 0 R/W A A7 A6 A5 A4 A3 A2 A1 A0 A D7 D6 D5 D4 D3 D2 D1 D0 A Start SMBus Device Address Byte (2Ch) ACK from aSC7611 Register Address Byte ACK from aSC7611 Register Data Byte ACK from aSC7611 Stop by Master Figure 3 Register Write 1 9 1 9 Register Address Pointer Set + (Figure 2.) without stop by Master S 0 1 0 1 1 0 0 R/W A D7 D6 D5 D4 D3 D2 D1 D0 N Re-start ACK from SMBus Device Address Byte (2Ch) aSC7611 Register Data Byte NACK from Master Stop by Master Figure 4 Register Read 1 SCL SDA S 0 1 0 1 1 0 0 R/W 9 1 9 A D7 D6 D5 D4 D3 D2 D1 D0 N Stop by Master Start SMBus Device Address Byte (2Ch) ACK from aSC7611 Register Data Byte NACK from Master Figure 5 Register Read When Read Address Already Set (c) Andigilog, Inc. 2006 - 10 www.andigilog.com October 2006 - 70A05007 aSC7611 Register Set Register Address Default Value (hex) 36 36 R/W Register Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Meas Duration 0 Meas Duration 0 Meas Duration 0 Meas Duration 0 04h 05h 06h 07h 08h 09h 0Eh 0Fh 10h 11h 12h 13h 14h 15h 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh R/W R/W R/W R/W R R/W R R/W R R R R R R R R R R R R R R R R R R Tach 1 Configuration Tach 2 Configuration Tach 3 Configuration Tach 4 Configuration Vccp (LS Byte) Configuration Zone 3 Temperature (LS Byte) One shot Measurement Zone 1 Temperature (LS Byte) 3.3V (LS Byte) 5V (LS Byte) 2.5V (LS Byte) 12V (LS Byte) Zone 2 Temperature (LS Byte) 2.5V (MS Byte) Vccp (MS Byte) 3.3 V (MS Byte) 5V (MS Byte) 12V (MS Byte) Zone 1 Temperature (MS Byte) Zone 2 Temperature (MS Byte) Zone 3 Temperature (MS Byte) Tach 1 LS Byte Tach 1 MS Byte Tach 2 LS Byte Tach 2 MS Byte 3-Wire Enable1 3-Wire Enable1 3-Wire Enable1 3-Wire Enable1 3-Wire Enable0 3-Wire Enable0 3-Wire Enable0 3-Wire Enable0 Meas Blank1 Meas Blank1 Meas Blank1 Meas Blank1 Meas Blank 0 Meas Blank 0 Meas Blank 0 Meas Blank 0 Meas Dwell 1 Meas Dwell 1 Meas Dwell 1 Meas Dwell 1 Meas Dwell 0 Meas Dwell 0 Meas Dwell 0 Meas Dwell 0 Meas Duration 1 Meas Duration 1 Meas Duration 1 Meas Duration 1 Lock Preliminary Specification - Subject to change without notice Preliminary Specification - Subject to change without notice 36 36 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 1 RES 1 RES 1 1 1 1 1 1 9 9 9 9 9 9 9 9 7 15 7 15 0 Run/ Stop 0 RES 0 0 0 0 0 0 8 8 8 8 8 8 8 8 6 14 6 14 X RES X RES X X X X X X 7 7 7 7 7 7 7 7 5 13 5 13 X RES X RES X X X X X X 6 6 6 6 6 6 6 6 4 12 4 12 X RES X RES X X X X X X 5 5 5 5 5 5 5 5 3 11 3 11 X RES X RES X X X X X X 4 4 4 4 4 4 4 4 2 10 2 10 X RES X RES X X X X X X 3 3 3 3 3 3 3 3 1 9 1 9 X RES X RES X X X X X X 2 2 2 2 2 2 2 2 0 8 0 8 (c) Andigilog, Inc. 2006 - 11 www.andigilog.com October 2006 - 70A05007 aSC7611 Register Address Default Value (hex) 00 00 00 00 FF FF FF FF FF FF 61 69 00 00 00 00 00 FF 00 FF 00 FF R/W Register Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 38h 39h 3Ah 3Eh 3Fh 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h R R R R R/W R/W R/W R/W R/W R/W R R R/W R R R R/W R/W R/W R/W R/W R/W Tach 3 LS Byte Tach 3 MS Byte Tach 4 LS Byte Tach 4 MS Byte Fan 1 Current PWM Duty Fan 2 Current PWM Duty Fan 3 Current PWM Duty Fan 1 Max Duty Cycle Fan 2 Max Duty Cycle Fan 3 Max Duty Cycle Company ID Version/ Stepping Ready/Lock/ Start/Override Interrupt Status Register 1 Interrupt Status Register 2 VID0-4 2.5V Low Limit 2.5V High Limit Vccp Low Limit Vccp High Limit 3.3V Low Limit 3.3V High Limit 7 15 7 15 7 7 7 7 7 7 7 VER3 RES ERR ERR2 RES 7 7 7 7 7 7 6 14 6 14 6 6 6 6 6 6 6 VER2 RES ZN3 ERR1 RES 6 6 6 6 6 6 5 13 5 13 5 5 5 5 5 5 5 VER1 RES ZN2 FAN4 RES 5 5 5 5 5 5 4 12 4 12 4 4 4 4 4 4 4 VER0 RES ZN1 FAN3 VID4 4 4 4 4 4 4 3 11 3 11 3 3 3 3 3 3 3 STP3 OVRID 5V FAN2 VID3 3 3 3 3 3 3 2 10 2 10 2 2 2 2 2 2 2 STP2 READY 3.3V FAN1 VID2 2 2 2 2 2 2 1 9 1 9 1 1 1 1 1 1 1 STP1 LOCK VCCP RES VID1 1 1 1 1 1 1 0 8 0 8 0 0 0 0 0 0 0 STP0 START 2.5V 12V VID0 0 0 0 0 0 0 Lock Preliminary Specification - Subject to change without notice Preliminary Specification - Subject to change without notice (c) Andigilog, Inc. 2006 - 12 www.andigilog.com October 2006 - 70A05007 aSC7611 Register Address Default Value (hex) 00 FF 00 FF 81 7F 81 7F 81 7F FF FF FF FF FF FF FF FF 62 62 62 C3 X X X X R/W Register Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h 51h 52h 53h 54h 55h 56h 57h 58h 59h 5Ah 5Bh 5Ch 5Dh 5Eh 5Fh R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 5V Low Limit 5V High Limit 12V Low Limit 12V High Limit Zone 1 Low Temperature Zone 1 High Temperature Zone 2 Low Temperature Zone 2 High Temperature Zone 3 Low Temperature Zone 3 High Temperature Tach 1 Minimum LS Byte Tach 1 Minimum MS Byte Tach 2 Minimum LS Byte Tach 2 Minimum MS Byte Tach 3 Minimum LS Byte Tach 3 Minimum MS Byte Tach 4 Minimum LS Byte Tach 4 Minimum MS Byte Fan 1 Configuration Fan 2 Configuration Fan 3 Configuration Zone 1 Range/ Fan 1 Frequency 7 7 7 7 7 7 7 7 7 7 7 15 7 15 7 15 7 15 ZON2 ZON2 ZON2 RAN3 6 6 6 6 6 6 6 6 6 6 6 14 6 14 6 14 6 14 ZON1 ZON1 ZON1 RAN2 5 5 5 5 5 5 5 5 5 5 5 13 5 13 5 13 5 13 ZON0 ZON0 ZON0 RAN1 4 4 4 4 4 4 4 4 4 4 4 12 4 12 4 12 4 12 INV INV INV RAN0 3 3 3 3 3 3 3 3 3 3 3 11 3 11 3 11 3 11 RES RES RES HLFRQ 2 2 2 2 2 2 2 2 2 2 2 10 2 10 2 10 2 10 SPIN2 SPIN2 SPIN2 FRQ2 1 1 1 1 1 1 1 1 1 1 1 9 1 9 1 9 1 9 SPIN1 SPIN1 SPIN1 FRQ1 0 0 0 0 0 0 0 0 0 0 0 8 0 8 0 8 0 8 SPIN0 SPIN0 SPIN0 FRQ0 Lock Preliminary Specification - Subject to change without notice Preliminary Specification - Subject to change without notice (c) Andigilog, Inc. 2006 - 13 www.andigilog.com October 2006 - 70A05007 aSC7611 Register Address Default Value (hex) C3 R/W Register Name Zone 2 Range/ Fan 2 Frequency Zone 3 Range/ Fan 3 Frequency Min/Off, Zone 1 Spike Smoothing Zone2 / Zone 3 Spike Smoothing Fan 1 PWM Minimum Fan 2 PWM Minimum Fan 3 PWM Minimum Zone 1 Fan Temp Limit Zone 2 Fan Temp Limit Zone 3 Fan Temp Limit Zone 1 Temp Absolute Limit Zone 2 Temp Absolute Limit Zone 3 Temp Absolute Limit Zone 1, Zone 2 Hysteresis Zone 3 Hysteresis XOR Tree Enable Fan Spin-up Mode Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) 60h R/W RAN3 RAN2 RAN1 RAN0 HLFRQ FRQ2 FRQ1 FRQ0 61h R/W RAN3 RAN2 RAN1 RAN0 HLFRQ FRQ2 FRQ1 FRQ0 C3 62h R/W OFF3 OFF2 OFF1 RES ZN1E ZN1-2 ZN1-1 ZN1-0 00 63h R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W ZN2E 7 7 7 7 7 7 7 7 7 H1-3 H3-3 RES Tach4 Disable ZN2-2 6 6 6 6 6 6 6 6 6 H1-2 H3-2 RES Tach3/4 Disable ZN2-1 5 5 5 5 5 5 5 5 5 H1-1 H3-1 RES Tach2 Disable ZN2-0 4 4 4 4 4 4 4 4 4 H1-0 H3-0 RES Tach1 Disable ZN3E 3 3 3 3 3 3 3 3 3 H2-3 RES RES RES ZN3-2 2 2 2 2 2 2 2 2 2 H2-2 RES RES PWM3SU ZN3-1 1 1 1 1 1 1 1 1 1 H2-1 RES RES PWM2SU ZN3-0 0 0 0 0 0 0 0 0 0 H2-0 RES XEN PWM1SU 00 80 80 80 5A 5A 5A 64 64 64 44 40 00 00 Lock X X X X Preliminary Specification - Subject to change without notice Preliminary Specification - Subject to change without notice 64h 65h 66h 67h 68h 69h 6Ah 6Bh 6Ch 6Dh 6Eh 6Fh 75h X X X X X X X X X X X X X Note: Reserved bits will always return 0 when read, X-bits in readings may be ignored. (c) Andigilog, Inc. 2006 - 14 www.andigilog.com October 2006 - 70A05007 aSC7611 Temperature Measurement Temperatures are measured with a precision Delta-VBE methodology converted to a digital temperature reading by a 10-bit sigma-delta converter. The user may set limits on these readings to be continuously monitored and alarm bits set when they are exceeded. Separately, the measurements are also delivered to the automatic fan control system to adjust fan speed. The following registers contain the readings from the internal and remote sensors. Registers 25-10h, 26-15h and 27-0Eh: Zone Temperature Readings (10-Bit, 2's Complement Reporting) Register Address 25h 10h 26h Read/ Write R R R R R R Register Name Zone 1 Temperature (MS Byte) Zone 1 Temperature (LS Byte) Zone 2 Temperature (MS Byte) Zone 2 Temperature (LS Byte) Zone 3 Temperature (MS Byte) Zone 3 Temperature (LS Byte) Bit 7 (MSB) 9 1 9 1 9 1 Bit 6 8 0 8 0 8 0 Bit 5 7 X 7 X 7 X Bit 4 6 X 6 X 6 X Bit 3 5 X 5 X 5 X Bit 2 4 X 4 X 4 X Bit 1 3 X 3 X 3 X Bit 0 (LSB) 2 X 2 X 2 X Default Value 00 00 00 Preliminary Specification - Subject to change without notice Preliminary Specification - Subject to change without notice 15h 27h 0Eh 00 00 00 The Zone Temperature registers reflect the current temperature of the internal and remote diodes. Processor (Zone 1) Temp register reports the temperature measured by the thermal diode connected to the Remote 1- and Remote 1+ pins. Internal (Zone 2) Temp register reports the temperature measured by the internal (junction) temperature sensor. Remote 2 (Zone 3) Temp register reports the temperature measured by the thermal diode connected to the second set of Remote 2and Remote 2+ pins. Temperatures are represented as 10 bit, 2's complement, signed numbers, in degrees Celsius, as shown below in Table 1. The Temperature Reading register will return a value of 8000h if the remote diode pins are not used by the board designer or are not functioning properly. This reading will cause the zone limit bits (bits 4 and 6) in the Interrupt Status Register (41h) and the remote diode fault status bit (bits 6 and 7) in the Interrupt Status Register 2 (42h) to be set. These registers are readonly - a write to these registers has no effect. Digital Output (2's Complement) Temperature +125C +100C +50C +25C +10C +1.75C +0.25C 0C -1.75C -55C High Byte 10-Bit Resolution Low Byte Ignore XX XX XX XX XX XX XX XX XX XX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX 0111 0110 0011 0001 0000 0000 0000 0000 1111 1100 1101 0100 0010 1001 1010 0001 0000 0000 1110 1001 00 00 00 00 00 11 01 00 01 00 Table 1 Relationship between Temperature and 2's Complement Digital Output, -55C to +125C (c) Andigilog, Inc. 2006 - 15 www.andigilog.com October 2006 - 70A05007 aSC7611 Temperature Measurement Configuration Registers 09h and 0Fh: Measurement Configuration Register Address 09h 0Fh Read/ Write R/W R/W Register Name Configuration One shot Measurement Bit 7 (MSB) RES RES Bit 6 Run/ Stop RES Bit 5 RES RES Bit 4 RES RES Bit 3 RES RES Bit 2 RES RES Bit 1 RES RES Bit 0 (LSB) RES RES Default Value 00 00 A write to the One-shot Measurement register address 0Fh initiates a temperature measurement when aSC7611 is in Stop mode (set by bit 6 of register 09h) and returns to that mode after all three temperature and five voltage measurements are complete. Bit 0:5 Name Reserved Run/Stop Reserved R/W R/W R/W R/W Default 0 0 0 Reserved Description Preliminary Specification - Subject to change without notice Preliminary Specification - Subject to change without notice 6 7 Measurement system run(default) or stop, places aSC7611 in a low-power or standby mode. Reserved Table 2 Configuration Register [09h] bits Voltage Measurement and Limits Register 20-24h: Voltage Reading Register Address 20h 21h 22h 23h 24h Read/ Write R R R R R Register Name 2.5V VCCP 3.3V 5V 12V Bit 7 (MSB) 7 7 7 7 7 Bit 6 6 6 6 6 6 Bit 5 5 5 5 5 5 Bit 4 4 4 4 4 4 Bit 3 3 3 3 3 3 Bit 2 2 2 2 2 2 Bit 1 1 1 1 1 1 Bit 0 (LSB) 0 0 0 0 0 Default Value 00 00 00 00 00 The Register Names define the typical input voltage at which the reading is 3/4 full scale or C0h. The Voltage Reading registers are updated automatically by the aSC7611 at a minimum frequency of 4Hz. These registers are read only - a write to these registers has no effect. Register 44-4Dh: Voltage Limit Registers Register Address 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh Read/ Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Register Name 2.5V Low Limit 2.5V High Limit VCCP Low Limit VCCP High Limit 3.3V Low Limit 3.3V High Limit 5V Low Limit 5V High Limit 12V Low Limit 12V High Limit Bit 7 (MSB) 7 7 7 7 7 7 7 7 7 7 Bit 6 6 6 6 6 6 6 6 6 6 6 Bit 5 5 5 5 5 5 5 5 5 5 5 Bit 4 4 4 4 4 4 4 4 4 4 4 Bit 3 3 3 3 3 3 3 3 3 3 3 Bit 2 2 2 2 2 2 2 2 2 2 2 Bit 1 1 1 1 1 1 1 1 1 1 1 Bit 0 (LSB) 0 0 0 0 0 0 0 0 0 0 Default Value 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh If a voltage input either exceeds the value set in the voltage high limit register or falls below the value set in the voltage low limit register, the corresponding bit will be set automatically by the aSC7611 in the interrupt status registers (41-42h). Voltages are presented in the registers at 3/4 of full-scale for the nominal voltage, meaning that at nominal voltage, each input will be C0h, as shown in Table 3. Note that 3.3V input is Vdd and is not allowed to go below 3.0V during normal operation. (c) Andigilog, Inc. 2006 - 16 www.andigilog.com October 2006 - 70A05007 aSC7611 Setting the Ready/Lock/Start/Override register Lock bit has no effect on these registers. Input Nominal Voltage 2.5V 2.25V 3.3V 5.0V 12.0V Register Reading at Nominal Voltage C0h C0h C0h C0h C0h Maximum Voltage 3.32V 3.00V 4.38V 6.64V 16.00V Register Reading at Maximum Voltage FFh FFh FFh FFh FFh Minimum Voltage 0V 0V 3.0V 0V 0V Register Reading at Minimum Voltage 00h 00h AFh 00h 00h 2.5V VCCP 3.3V 5V 12V Table 3 Voltage Limits vs Register Setting Status Registers Preliminary Specification - Subject to change without notice Preliminary Specification - Subject to change without notice Register 41h: Interrupt Status Register 1 Register Address 41h Read/ Write R Register Name Interrupt Status 1 Bit 7 (MSB) ERR Bit 6 ZN3 Bit 5 ZN2 Bit 4 ZN1 Bit 3 5V Bit 2 3.3V Bit 1 VCCP Bit 0 (LSB) 2.5V Default Value 00 The Interrupt Status Register 1 bits will be automatically set, by the aSC7611, whenever a fault condition is detected. A fault condition is detected whenever a measured value is outside the window set by its limit registers. ZN1 bit will be set when a diode fault condition, such as an open or short, is detected. More than one fault may be indicated in the interrupt register when read. The register will hold a set bit(s) until the event is read by software. The contents of this register will be cleared (set to 0) automatically by the aSC7611 after it is read by software, if the fault condition no longer exists. Once set, the Interrupt Status Register 1 bits will remain set until a read event occurs, even if the fault condition no longer exists. This register is read-only - a write to this register has no effect. Bit 0 Name 2.5V Limits Exceeded Vccp Limits Exceeded 3.3V Limits Exceeded 5V Limits Exceeded R/W R Default 0 Description The aSC7611 automatically sets this bit to 1 when the 2.5V input voltage is less than or equal to the limit set in the 2.5V Low Limit register or greater than the limit set in the 2.5V High Limit register. The aSC7611 automatically sets this bit to 1 when the VCCP input voltage is less than or equal to the limit set in the VCCP Low Limit register or greater than the limit set in the VCCP High Limit register. The aSC7611 automatically sets this bit to 1 when the 3.3V input voltage is less than or equal to the limit set in the 3.3V Low Limit register or greater than the limit set in the 3.3V High Limit register. The aSC7611 automatically sets this bit to 1 when the 5V input voltage is less than or equal to the limit set in the 5V Low Limit register or greater than the limit set in the 5V High Limit register. The aSC7611 automatically sets this bit to 1 when the temperature input measured by the Remote1- and Remote1+ inputs is less than or equal to the limit set in the Processor (Zone 1) Low Temp register or more than the limit set in the Processor (Zone 1) High Temp register. This bit will be set when a diode fault is detected. The aSC7611 automatically sets this bit to 1 when the temperature input measured by the internal temperature sensor is less than or equal to the limit set in the thermal (Zone 2) Low Temp register or greater than the limit set in the Internal (Zone 2) High Temp register. The aSC7611 automatically sets this bit to 1 when the temperature input measured by the second remote temperature sensor is less than or equal to the limit set in the thermal (Zone 3) Low Temp register or greater than the limit set in the Internal (Zone 3) High Temp register. If there is a set bit in Status Register 2, this bit will be set to 1. 1 R 0 2 R 0 3 R 0 4 Zone 1 Limit Exceeded R 0 5 Zone 2 Limit Exceeded R 0 6 Zone 3 Limit Exceeded Error in Status Register 2 R 0 7 R 0 Table 4 Interrupt Status Register 1 (c) Andigilog, Inc. 2006 - 17 www.andigilog.com October 2006 - 70A05007 aSC7611 Register 42h: Interrupt Status Register 2 Register Address 42h Read/ Write R Register Name Bit 7 (MSB) ERR2 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) 12V Default Value 00 Interrupt Status 2 ERR1 FAN4 FAN3 FAN2 FAN1 RES The Interrupt Status Register 2 bits will be automatically set, by the aSC7611, whenever a fault condition is detected. Interrupt Status Register 2 identifies faults caused by temperature sensor error, fan speed dropping below minimum set by the tachometer minimum register. Interrupt Status Register 2 will hold a set bit until the event is read by software. The contents of this register will be cleared (set to 0) automatically by the aSC7611 after it is read by software, if fault condition no longer exists. Once set, the Interrupt Status Register 2 bits will remain set until a read event occurs, even if the fault no longer exists. This register is read-only - a write to this register has no effect. Bit Name 12V Limits Exceeded RES FAN 1 STALLED FAN 2 STALLED FAN 3 STALLED FAN 4 STALLED Remote Diode 1 Fault Remote Diode 2 Fault R/W R R R R R R R Default 0 0 0 0 0 0 0 Description The aSC7611 automatically sets this bit to 1 when the 12V input voltage is less than or equal to the limit set in the 12V Low Limit register or greater than the limit set in the 12V High Limit register. Reserved The aSC7611 automatically sets this bit to 1 when the TACH 1 input reading is above the count value set in the Tach 1 Minimum MSB and LSB registers. The aSC7611 automatically sets this bit to 1 when the TACH 2 input reading is above the count value set in the Tach 2 Minimum MSB and LSB registers. The aSC7611 automatically sets this bit to 1 when the TACH 3 input reading is above the count value set in the Tach 3 Minimum MSB and LSB registers. The aSC7611 automatically sets this bit to 1 when the TACH 4 input reading is above the count value set in the Tach 4 Minimum MSB and LSB registers. The aSC7611 automatically sets this bit to 1 when there is an open circuit fault on the Remote1+ or Remote1- thermal diode input pins. A diode fault will also set bit 4 Zone 1 Limit bit, of Interrupt Status Register 1. The aSC7611 automatically sets this bit to 1 when there is an open circuit fault on the Remote2+ or Remote2- thermal diode input pins. A diode fault will also set bit 6 Zone 3 Limit bit, of Interrupt Status Register 1. Preliminary Specification - Subject to change without notice Preliminary Specification - Subject to change without notice 0 1 2 3 4 5 6 7 R 0 Table 5 Interrupt Status Register 2 Register 43h: VID Register Register Address 43h Read/ Write R Register Name VID0-4 Bit 7 (MSB) RES Bit 6 RES Bit 5 RES Bit 4 VID4 Bit 3 VID3 Bit 2 VID2 Bit 1 VID1 Bit 0 (LSB) VID0 Default Value 00 The VID register contains the values of aSC7611 VID0-VID4 input pins. This register indicates the status of the VID lines that interconnect the processor to the Voltage Regulator Module (VRM). Software uses the information in this register to determine the voltage that the processor is designed to operate at. With this information, software can then dynamically determine the correct values to place in the VCCP Low Limit and VCCP High Limit registers. This register is read-only - a write to this register has no effect. Tachometer Measurement and Configuration Register 28-2Fh: Fan Tachometer Reading Register Address 28h 29h 2Ah 2Bh 2Ch Read/ Write R R R R R Register Name Tach 1 LS Byte Tach 1 MS Byte Tach 2 LS Byte Tach 2 MS Byte Tach 3 LS Byte Bit 7 (MSB) 7 15 7 15 7 Bit 6 6 14 6 14 6 Bit 5 5 13 5 13 5 Bit 4 4 12 4 12 4 Bit 3 3 11 3 11 3 Bit 2 2 10 2 10 2 Bit 1 1 9 1 9 1 Bit 0 (LSB) 0 8 0 8 0 Default Value N/A N/A N/A N/A N/A (c) Andigilog, Inc. 2006 - 18 www.andigilog.com October 2006 - 70A05007 aSC7611 Register Address 2Dh 2Eh 2Fh Read/ Write R R R Register Name Tach 3 MS Byte Tach 4 LS Byte Tach 4 MS Byte Bit 7 (MSB) 15 7 15 Bit 6 14 6 14 Bit 5 13 5 13 Bit 4 12 4 12 Bit 3 11 3 11 Bit 2 10 2 10 Bit 1 9 1 9 Bit 0 (LSB) 8 0 8 Default Value N/A N/A N/A The Fan Tachometer Reading registers contains the number of 11.111s periods (90 kHz) between full fan revolutions. The results are based on the time interval of two tachometer pulses, since most fans produce two tachometer pulses per full revolution. These registers will be updated at least once every second. Common interpretation of tachometer readings is to take the binary period measurement and convert it to RPM. This may be done by applying the formula: RPM = (90,000 x 60)/(Decimal Equivalent of binary Tach Reading) The value, for each fan, is represented by a 16-bit unsigned number. The Fan Tachometer Reading registers will always return an accurate fan tachometer measurement, even when a fan is disabled or non-functional, however, if PWM commands for a fan (register 30h to 32h) is zero, tach measurements are suspended and the last reading may remain in the register. FF FFh indicates that the fan is not spinning, or that the tachometer input is not connected to a valid signal. This value may be FF FEh or FF FCh if Measurement Duration, bits 1:0 of register 3A-3Dh are set to 01 or 00, respectively. These registers are read-only - a write to these registers has no effect. When the LSByte of the aSC7611 16-bit register is read, the other byte (MSByte) is latched at the current value until it is read. At the end of the MSByte read the Fan Tachometer Reading registers are updated. During spin-up, the PWM duty cycle reported is 0%. Preliminary Specification - Subject to change without notice Preliminary Specification - Subject to change without notice Registers 54-5Bh: Fan Tachometer Limits Register Address 54h 55h 56h 57h 58h 59h 5Ah 5Bh Read/ Write R/W R/W R/W R/W R/W R/W R/W R/W Register Name Tach 1 Minimum LS Byte Tach 1 Minimum MS Byte Tach 2 Minimum LS Byte Tach 2 Minimum MS Byte Tach 3 Minimum LS Byte Tach 3 Minimum MS Byte Tach 4 Minimum LS Byte Tach 4 Minimum MS Byte Bit 7 (MSB) 7 15 7 15 7 15 7 15 Bit 6 6 14 6 14 6 14 6 14 Bit 5 5 13 5 13 5 13 5 13 Bit 4 4 12 4 12 4 12 4 12 Bit 3 3 11 3 11 3 11 3 11 Bit 2 2 10 2 10 2 10 2 10 Bit 1 1 9 1 9 1 9 1 9 Bit 0 (LSB) 0 8 0 8 0 8 0 8 Default Value FF FF FF FF FF FF FF FF The Fan Tachometer Low Limit registers indicate the tachometer reading under which the corresponding bit will be set in the Interrupt Status Register 2 register. In Auto Fan Control mode, the fan can run at low speeds, so care should be taken in software to ensure that the limit is high enough not to cause sporadic alerts. The fan tachometer will not cause a bit to be set in Interrupt Status Register 2 if the current value in Current PWM Duty registers (30h to 32h) is 00h or if the fan is disabled via the Fan Configuration Register. Interrupts will not be generated for a fan if its minimum is set to FF FFh except for timeout. Setting the Ready/Lock/Start/Override register Lock bit has no effect on these registers. Given the relative insignificance of Bit 0 and Bit 1, these bits could be programmed to designate the physical location of the fan generating the tachometer signal, as follows: Register Name CPU Cooler Memory Controller Chassis Front Chassis Rear (c) Andigilog, Inc. 2006 Bit 1 0 0 1 1 Bit 0 (LSB) 0 1 0 1 October 2006 - 70A05007 - 19 www.andigilog.com aSC7611 Register 04-07h: Fan Tachometer Measurement Configuration Register Address 04h Read/ Write R/W Register Name Tach 1 Configuration Tach 2 Configuration Tach 3 Configuration Tach 4 Configuration Bit 7 (MSB) 3-Wire Enable1 3-Wire Enable1 3-Wire Enable1 3-Wire Enable1 Bit 6 Bit 5 Meas Blank 1 Meas Blank 1 Meas Blank 1 Meas Blank 1 Bit 4 Meas Blank 0 Meas Blank 0 Meas Blank 0 Meas Blank 0 Bit 3 Meas Dwell 1 Meas Dwell 1 Meas Dwell 1 Meas Dwell 1 Bit 2 Meas Dwell 0 Meas Dwell 0 Meas Dwell 0 Meas Dwell 0 Bit 1 Meas Duration 1 Meas Duration 1 Meas Duration 1 Meas Duration 1 Bit 0 (LSB) Meas Duration 0 Meas Duration 0 Meas Duration 0 Meas Duration 0 Default Value 36 3-Wire Enable0 3-Wire Enable0 3-Wire Enable0 3-Wire Enable0 05h R/W 36 06h R/W 36 07h R/W 36 Preliminary Specification - Subject to change without notice Preliminary Specification - Subject to change without notice The Fan Tachometer Configuration registers contain the settings that define the modes of measurement of the Tachometer input signals. The user is allowed to disable a tachometer measurement or to request PWM stretching, in the case of a 3wire fan. Also, the rate, start-up and period of measurements within a fan rotation cycle may be selected. The table below describes the controls. Bit Name R/W Default Description The amount of fan rotation used for the tach measurement. Assumes 2 pulse periods per rotation of fan. 1:0 Measurement Duration R/W 10 00: 1/4 Rotation - Tach Count x4 = Reported Valu 01: 1/2 Rotation - Tach Count x2 = Reported Value 10: 1 Rotation - Tach Count x1 = Reported Value (default) 11: 2 Rotation - Tach Count x1 = Reported Value Delay between Tach Measurements 3:2 Measurement Dwell R/W 01 00: 100 ms 01: 300 ms (default) 10: 500 ms 11: 728 ms In 3-wire fan mode, a delay is needed to assure that the tach input has stabilized after the PWM has been set to 100% 5:4 Measurement Blank R/W 11 00: 11.1 s 01: 22.2 s 10: 33.3 s 11: 44.4 s (default) For 3-Wire mode, the PWM output will be forced to 100% when the tach measurement is being processed. Each fan has a 3Wire Mode control that will behave as indicated in this table: HLFRQ (5Fh-61h) 0 0 7:6 3-Wire Enable R/W 00 0 0 1 1 1 1 3-Wire Enable (7:6) 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 3-Wire Mode Enabled Enabled Enabled Disabled Disabled Disabled Enabled Disabled Table 6 Tachometer Configuration Register (c) Andigilog, Inc. 2006 - 20 www.andigilog.com October 2006 - 70A05007 aSC7611 Automatic Fan Control Auto Fan Control Operating Mode The aSC7611 includes the circuitry for automatic fan control. In Auto Fan Mode, the aSC7611 will automatically adjust the PWM duty cycle of the PWM output. PWM outputs are assigned to a thermal zone based on the fan configuration registers. At any time, the temperature of a zone exceeds its Absolute Limit, all PWM outputs will go to 100% duty cycle to provide maximum cooling to the system. Fan Temp Limit less Hysteresis Fan Temp Limit Fan Temp Limit plus Range Absolute Limit Hysteresis (0 C to 15 C) Range (2 C to 80 C) y earl le lin Cyc emp arly line Duty hT WM sing wit ty Cycle h Temp P t u ea g wi MD Incr PW creasin De Preliminary Specification - Subject to change without notice Preliminary Specification - Subject to change without notice 100% PWM Set to Minimum PWM % User Choice: Set to Minimum or Off PWM Set to Off 0% Temperature PWM set to Off or Minimum Below this Temperature Linear Control Range PWM 100% Example Temperature C 5 C Hysteresis 45 50 8 C Range 58 80 Off/ Min% 100% Min% Minimum PWM set to 50%, fan speed increases linearly beyond 50 C but will not return to off until it has gone below Fan Temp Limit by the 5 C Hysteresis setting to 45C. PWM % Figure 6 Automatic Fan Speed Control Example Example for PWM1 assigned to Zone 1: * * * Zone 1 Fan Temp Limit (Register 67h) is set to 50C (32h). Zone 1 Range (Register 5Fh) is set to 8C (6xh). Fan PWM Minimum (Register 64h) is set to 50% (80h). In this case, the PWM duty cycle will be 50% at 50C. Since (Zone 1 Fan Temp Limit) + (Zone 1 Range) = 50C + 8C = 58C, the fan will run at 100% duty cycle when the temperature of the Zone 1 sensor reaches 58C. Since the midpoint of the fan control range is 54C, and the median duty cycle is 75% (Halfway between the PWM Minimum and 100%), PWM1 duty cycle would be 75% at 54C. Above (Zone 1 Fan Temp Limit) + (Zone 1 Range), the duty cycle will be 100%. - 21 www.andigilog.com (c) Andigilog, Inc. 2006 October 2006 - 70A05007 aSC7611 Automatic Fan Speed Control using Maximum PWM Setting The previously described and illustrated mode had no restriction on the maximum PWM setting. It is useful to limit the maximum PWM command sent to the fan in order to minimize the acoustic impact. The Maximum PWM setting will clamp the automatic fan PWM command at a user selected value. The Absolute Limit setting will still cause the PWM command to be 100% and that will remain until the temperature falls below the Absolute Limit temperature by an amount equal to the hysteresis setting. This will minimize the acoustic impact of having a temperature moving back and forth close to the Absolute Limit. The Absolute Limit may be set above or below the Fan Temp Limit plus Range. The PWM value will be overridden and will follow the hysteresis curve in either case, but the acoustic impact will be different, running the fan to 100% PWM at a lower temperature, but enhancing the cooling effect. Absolute Limit set on the low end is shown in Figure 6. Setting it above is shown in Figure 8. It is important to consider the combination of Fan Temp Limit, Range, Maximum PWM and Absolute Limit and their impact on cooling and acoustics. In addition, the capability to operate a fan from a combination of thermal zones allows a compound linear slope to be achieved for further optimization. Preliminary Specification - Subject to change without notice Preliminary Specification - Subject to change without notice Fan Temp Limit less Hysteresis Fan Temp Limit Absolute Limit Fan Temp Limit plus Range Hysteresis (0 C to 15 C) Range (2 C to 80 C) Hysteresis (0 C to 15 C) Maximum PWM % Fan Speed Fan Set to Minimum Fan Set to Off arly line e ycl emp T arly ty C ine Du g with le l Temp M in yc th PW reas i ty C Du sing w Inc M ea PW ecr D Temperature PWM set to Off Linear Control Range PWM 100% Figure 7 Fan Control with Absolute Limit Set below Fan Temp Limit Plus Range (c) Andigilog, Inc. 2006 - 22 www.andigilog.com October 2006 - 70A05007 aSC7611 Fan Temp Limit less Hysteresis Fan Temp Limit Fan Temp Limit plus Range Absolute Limit Hysteresis (0 C to 15 C) Range (2 C to 80 C) Hysteresis (0 C to 15 C) Maximum PWM % Fan Speed Fan Set to Minimum Fan Set to Off arly ine le l m p yc e rly T ty C nea Du g with e li Temp Mn ycl th PW reasi i ty C Du sing w Inc M a PW ecre D Preliminary Specification - Subject to change without notice Preliminary Specification - Subject to change without notice Temperature PWM set to Off Linear Control Range PWM 100% Figure 8 Fan Control with Absolute Limit Set above Fan Temp Limit Plus Range Auto Fan Mode Initiated End Polling Cycle No Min Speed or Spin-Up Time Met? End Fan Spin Up Begin Polling Cycle Yes Yes Fan Spinning Up? No Override PWM Output to 100% Yes Temp >= AbsLimit? No Set Fan Output to Max PWM Set Fan Output to 0% Set fan output to auto fan mode minimum speed No Below Hysteresis? Yes Yes PWM= 100%? No PWM= No No Below Hysteresis? Yes Yes (Minimum Speed) Set Fan Output to 100% Begin Fan Spin up Yes Fan Output at 0%? No Set fan speed based on Auto Fan Range Algorithm Fan Output At 0%? Yes No Figure 9 Automatic Fan Control Algorithm (c) Andigilog, Inc. 2006 - 23 www.andigilog.com October 2006 - 70A05007 aSC7611 Fan Register Device Set-Up The BIOS will follow the following steps to configure the fan registers on the aSC7611. The registers corresponding to each function are listed. All steps may not be necessary if default values are acceptable. Regardless of all changes made by the BIOS to the fan limit and parameter registers during configuration, the aSC7611 will continue to operate based on default values until the START bit (bit 0), in the Ready/Lock/Start/Override register (address 40h), is set. Once the fan mode is updated, by setting the START bit to 1, the aSC7611 will operate using the values that were set by the BIOS in the fan control limit and parameter registers (address in the range 5Ch through 75h). 1. Set limits and parameters (not necessarily in this order): * * * * [5F-61h] Set PWM frequency for the fan and auto fan control range for each zone. [62-63h] Set spike smoothing and min/off. [5C-5Eh] Set the fan spin-up delay. [75h] Set PWM spin-up mode to terminate after time set in [5Ch]. Value = 00h instead of default 01h. [5Ch] Match fan with a corresponding thermal zone. [67-69h] Set the fan temperature limits. [6A-6Ch] Set the temperature absolute limits. [64-66h] Set the PWM minimum duty cycle. [6D-6Eh] Set the temperature hysteresis values. Preliminary Specification - Subject to change without notice Preliminary Specification - Subject to change without notice * * * * * 2. [40h] Set bit 0 (START) to update fan control and limit register values and start fan control based on these new values. [40h] (Optional) Set bit 1 (LOCK) to lock the fan limit and parameter registers. WARNING: this is a non-reversible change in state and locks out further change in critical fan control parameters until power is removed from the aSC7611. Register 5F-61h: Auto Fan Speed Range, PWM Frequency Register Address 5Fh 60h 61h Read/ Write R/W R/W R/W Register Name Zone 1 Range Fan1 Frequency Zone 2 Range/ Fan 2 Frequency Zone 3 Range/ Fan 3 Frequency Bit 7 (MSB) RAN3 RAN3 RAN3 Bit 6 RAN2 RAN2 RAN2 Bit 5 RAN1 RAN1 RAN1 Bit 4 RAN0 RAN0 RAN0 Bit 3 HLFRQ HLFRQ HLFRQ Bit 2 FRQ2 FRQ2 FRQ2 Bit 1 FRQ1 FRQ1 FRQ1 Bit 0 (LSB) FRQ0 FRQ0 FRQ0 Default Value C3 C3 C3 Lock X X X In Auto Fan Mode, when the temperature for a zone is above the Temperature Limit (Registers 67-69h) and below its Absolute Temperature Limit (Registers 6A-6Ch), the speed of a fan assigned to that zone is determined as follows: When the temperature reaches the Fan Temp Limit for a zone, the PWM output assigned to that zone will be Fan PWM Minimum. Between Fan Temp Limit and (Fan Temp Limit + Range), the PWM duty cycle will increase linearly according to the temperature as shown in the figure below. The PWM duty cycle will be 100% at (Fan Temp Limit + Range). PWM frequency - FRQ[3:0] and HLFRQ The PWM frequency bits [3:0] determine the PWM frequency for the fan. The aSC7611 has high and low frequency ranges for the PWM outputs that are controlled by the HLFRQ bit. PWM Frequency Selection (Default = 0011 30 Hz). (c) Andigilog, Inc. 2006 - 24 www.andigilog.com October 2006 - 70A05007 aSC7611 HLFRQ 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FRQ [2:0] 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 PWM Frequency ~10 Hz ~15 Hz ~23 Hz ~30 Hz (Default) ~38 Hz ~47 Hz ~62 Hz ~94 Hz ~23 kHz ~24 kHz ~25 kHz Preliminary Specification - Subject to change without notice Preliminary Specification - Subject to change without notice ~26 kHz ~27 kHz ~28 kHz ~29 kHz ~30 kHz Table 7 Register Setting vs PWM Frequency RAN[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Linear Control Range (C) 2 2.5 3.33 4 5 6.67 8 10 13.33 16 20 26.67 32 (default) 40 53.33 80 Table 8 Zone Range Setting, RAN[3:0] This register becomes Read-Only when the Ready/Lock/Start/Override register Lock bit is set. Any further attempts to write to this register shall have no effect. After power up the default value is used for bits 3:0 of registers 5F-61h whenever the Ready/Lock/Start/Override register Start bit is cleared even though modifications to this register are possible. Register 40h: Ready/Lock/Start/Override Register Address 40h Read/ Write R/W Register Name Ready/Lock/Start/ Override Bit 7 (MSB) RES Bit 6 RES Bit 5 RES Bit 4 RES Bit 3 OVRID Bit 2 READY Bit 1 LOCK Bit 0 (LSB) START Default Value 00 (c) Andigilog, Inc. 2006 - 25 www.andigilog.com October 2006 - 70A05007 aSC7611 Bit Name R/W Default Description When software writes a 1 to this bit, the aSC7611 fan monitoring and PWM output control functions will use the values set in the fan control limit and parameter registers (addresses 30-32h and 5Fh through 61h). Before this bit is set, the aSC7611 will not update the used register values, the default values will remain in effect. Whenever this bit is set to 0, the aSC7611 fan monitoring and PWM output control functions use the default fan limits and parameters, regardless of the current values in the limit and parameter registers (addresses 30-32h and 5Fh through 61h). The aSC7611 will preserve the values currently stored in the limit and parameter registers when this bit set or cleared. This bit is not affected by the state of the Lock bit. It is expected that all limit and parameter registers will be set by BIOS or application software prior to setting this bit. 0 START R/W 0 1 LOCK R/W 0 Preliminary Specification - Subject to change without notice Setting this bit to 1 locks specified limit and parameter registers. WARNING: Once this bit is set, limit and parameter registers become read-only and will remain locked until the device is powered off. This register bit becomes read-only once it is set. The aSC7611 sets this bit automatically after the part is fully powered up, has completed the power-up-reset process, and after all A/D converters are properly functioning. If this bit is set to 1, all PWM outputs will go to 100% duty cycle regardless of whether or not the lock bit is set. The OVRID bit has precedence over the disabled mode. Therefore, when OVRID is set the PWM will go to 100% even if the PWM is in the disabled mode. Reserved Preliminary Specification - Subject to change without notice 2 READY R 0 3 4-7 OVRID RESERVED R/W R 0 0 Table 9 READY / LOCK / START / OVRID Settings Register 30-32h: Current PWM Duty Cycle Register Address 30h 31h 32h Read/ Write R/W R/W R/W Register Name Fan 1 Current PWM Duty Fan 2 Current PWM Duty Fan 3 Current PWM Duty Bit 7 (MSB) 7 7 7 Bit 6 6 6 6 Bit 5 5 5 5 Bit 4 4 4 4 Bit 3 3 3 3 Bit 2 2 2 2 Bit 1 1 1 1 Bit 0 (LSB) 0 0 0 Default Value FF FF FF The Current PWM Duty registers store the current duty cycle at each PWM output. At initial power-on, the PWM duty cycle is 100% and thus, when read, this register will return FFh. After the Ready/Lock/Start/Override register Start bit is set, this register and the PWM signals will be updated based on the algorithm described in the Auto Fan Control Operating Mode section. When Ready/Lock/Start/Override register Start bit is zero, default value (FFh) is used. When read, the Current PWM Duty registers return the current PWM duty cycle. These registers are read-only unless the fan is in manual (test) mode, in which case a write to these registers will directly control the PWM duty cycle for each fan. The PWM duty cycle is represented as shown in Table 10. If a 3-wire fan is being used and the option to enable 3-wire tach measurement is selected, the effective PWM duty cycle will be impacted by this feature. The 3-wire Enable setting will hold the PWM signal high for the period taken to make a tachometer reading. This period depends on the RPM and various tachometer measurement parameters. Overall impact is that lower PWM commands will be effectively increased and there may be acoustic effects. (c) Andigilog, Inc. 2006 - 26 www.andigilog.com October 2006 - 70A05007 aSC7611 Current PWM % 0% ~25% ~50% (Default) ~75% 100% Register Value Binary 0000 0100 1000 1100 1111 0000 0000 0000 0000 1111 Hex 00 40 80 C0 FF Table 10 Current PWM Duty Cycle Setting Preliminary Specification - Subject to change without notice Preliminary Specification - Subject to change without notice Register 4E-53h: Thermal Zone Temperature Limit Registers Register Address 4Eh 4Fh 50h 51h 52h 53h Read/ Write R/W R/W R/W R/W R/W R/W Register Name Zone 1 Low Temperature Zone 1 High Temperature Zone 2 Low Temperature Zone 2 High Temperature Zone 3 Low Temperature Zone 3 High Temperature Bit 7 (MSB) 7 7 7 7 7 7 Bit 6 6 6 6 6 6 6 Bit 5 5 5 5 5 5 5 Bit 4 4 4 4 4 4 4 Bit 3 3 3 3 3 3 3 Bit 2 2 2 2 2 2 2 Bit 1 1 1 1 1 1 1 Bit 0 (LSB) 0 0 0 0 0 0 Default Value 81 7F 81 7F 81 7F If an external temperature input or the internal temperature sensor either exceeds the value set in the corresponding high limit register or falls below the value set in the corresponding low limit register, the corresponding bit will be set automatically by the aSC7611 in the Interrupt Status Register 1 (41h). For example, if the temperature read from the Remote - and Remote + inputs exceeds the Zone 1 High Temp register limit setting, Interrupt Status Register 1 ZN1 bit will be set. The temperature limits in these registers are represented as 8 bit 2's complement, signed numbers in Celsius, as shown below in Table 11. Setting the Ready/Lock/Start/Override register Lock bit has no effect on these registers. Temperature Limit (2's Complement) 0111 0111 0111 0101 0011 0001 0000 1100 1000 1111 1111 1101 1010 0010 1001 0000 1110 0001 Temperature >127C +127C (Default High) +125C +90C +50C +25C 0C -50C -127C (Default Low) Table 11 Zone Temperature High- and Low-Limit Registers - 8-Bit Two's Complement (c) Andigilog, Inc. 2006 - 27 www.andigilog.com October 2006 - 70A05007 aSC7611 Register 5C-5Eh: Fan Thermal Zone Assignment and Spin-up Mode Register Address 5Ch 5Dh 5Eh Read/ Write R/W R/W R/W Register Name Fan 1 Configuration Fan 2 Configuration Fan 3 Configuration Bit 7 (MSB) ZON2 ZON2 ZON2 Bit 6 ZON1 ZON1 ZON1 Bit 5 ZON0 ZON0 ZON0 Bit 4 INV INV INV Bit 3 RES RES RES Bit 2 SPIN2 SPIN2 SPIN2 Bit 1 SPIN1 SPIN1 SPIN1 Bit 0 (LSB) SPIN0 SPIN0 SPIN0 Default Value 62 62 62 Lock X X X This register becomes read-only when the Ready/Lock/Start/Override register Lock bit is set. Any further attempts to write to this register shall have no effect. Bits [7:5] Zone/Mode Bits [7:5] of the Fan Configuration registers associate each fan with a temperature sensor. When in Auto Fan Mode the fan will be assigned to a zone, and its PWM duty cycle will be adjusted according to the temperature of that zone. If "Hottest" option is selected (110), the fan will be controlled by the the hottest of zones 1, 2 or 3. To determine the "hottest zone", the PWM level for each zone is calculated then the zone with the higher PWM value (not temperature) is selected. When in manual control mode, the Current PWM duty register (30-32h) become Read/Write. It is then possible to control the PWM outputs with software by writing to these registers. When the fan is disabled (100) the corresponding PWM output should be driven low (or high, if inverted). Zone 1: Remote Diode 1 (processor), Zone 2: Internal Sensor, Zone 3 : Remote Diode 2 Preliminary Specification - Subject to change without notice Preliminary Specification - Subject to change without notice Fan Configuration Fan on Zone 1 auto Fan on Zone 2 auto Fan on Zone 3 auto Fan always on full Fan disabled Fan controlled by hotter of Zones 2 or 3 Fan controlled by hottest of Zones 1, 2 or 3 Fan manually controlled (Test Mode) ZON[2:0] 000 001 010 011 100 101 110 111 Table 12 Fan Zone Setting Bit [4] PWM Invert Bit [4] inverts the PWM output. If set to 0, 100% duty cycle will yield an output that is always high. If set to 1, 100% duty cycle will yield an output that is always low. Bit [3] Reserved Bit [2:0] Spin Up Bits [2:0] specify the `spin up' time for the fan. When a fan is being started from a stationary state, the PWM output is held at 100% duty cycle for the time specified in the table below before scaling to a lower speed. Spin Up Time 0 ms 100 ms 250 ms 400 ms 700 ms 1000 ms 2000 ms 4000 ms SPIN[2:0] 000 001 010 011 100 101 110 111 Table 13 Fan Spin-Up Register (c) Andigilog, Inc. 2006 - 28 www.andigilog.com October 2006 - 70A05007 aSC7611 Register 62, 63h: Min/Off, Spike Smoothing Register Address 62h 63h Read/ Write R/W R/W Register Name Min/Off, Zone1 Spike Smoothing Zone2 Spike Smoothing Bit 7 (MSB) OFF3 ZN2E Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) ZN1-0 ZN3-0 Default Value 00 00 Lock OFF2 ZN2-2 OFF1 ZN2-1 RES ZN2-0 ZN1E ZN3E ZN1-2 ZN3-2 ZN1-1 ZN3-1 X X The OFF1-OFF3 (Bits 7 to 5) specifiy whether the duty cycle will be 0% or Minimum Fan Duty when the measured temperature falls below the Temperature LIMIT register setting (see Table 15 below). If the Remote pins are connected to a processor or chipset, instantaneous temperature spikes may be sampled by the aSC7611. Fan speed algorithm has two phases of filtering on temperature zone readings. First, a "No-Spike" value is created from the current temperature and three previous readings. This is an average of the two remaining values when the high and low values are removed. This is the temperature used to determine PWM and is always running. The second phase is a user specified filter and coefficient. This filter determines a smoothed temperature value, Smooth Ti, by taking the No-Spike Ti, subtracting the previous smoothed temperature, Smooth Ti-1, divided by 2^N and adding that to the previously smoothed temperature. N and GAIN are coefficients selected internally to provide the spike filter smoothing time constants shown in Table 14, designated ZN1-2:ZN1-0 for Zone 1, ZN2-2:ZN2-0 for Zone 2 and ZN3-2:ZN3-0 for Zone 3. For the current temperature reading Ti: No-Spike Ti = (Discard min and max of (Ti, Ti-1, Ti-2, Ti-3))/2 Smooth Ti = GAIN * (No-Spike Ti - Smooth Ti-1)/2N + Smooth Ti-1 If these spikes are not filtered, the CPU fan (if connected to aSC7611) may turn on prematurely or produce unpleasant noise. For this reason, any zone that is connected to a chipset or processor should have spike smoothing enabled. Individual system characteristics will determine how large this coefficient should be. When spike smoothing is enabled, the temperature reading registers will still reflect the current value of the temperature - not the "smoothed out" value. ZN1E, ZN2E and ZN3E enable temperature smoothing for zones 1, 2 and 3 respectively. ZN1-2, ZN1-1 and ZN1-0 control smoothing time for Zone 1. ZN2-2, ZN2-1 and ZN2-0 control smoothing time for Zone 2. ZN3-2, ZN3-1 and ZN3-0 control smoothing time for Zone 3. Preliminary Specification - Subject to change without notice Preliminary Specification - Subject to change without notice These registers become read-only when the Ready/Lock/Start/Override register Lock bit is set. Any further attempts to write to these registers shall have no effect. 60 50 40 30 20 10 0 1 2 3 4 5 6 7 8 9 10 11 12 Figure 10 Representation of What Temperature Is Passed to the aSC7611 Auto Fan Control with (green) and without (red dashed) Spike Smoothing (c) Andigilog, Inc. 2006 - 29 www.andigilog.com October 2006 - 70A05007 aSC7611 Spike Smoothing Time 35 seconds 17.6 seconds 11.8 seconds 7.0 seconds 4.4 seconds 3.0 seconds 1.6 seconds 0.8 seconds ZNn-[2:0] 000 001 010 011 100 101 110 111 Table 14 Spike Smoothing for ZN1 to ZN3 Preliminary Specification - Subject to change without notice Preliminary Specification - Subject to change without notice PWM Action At 0% duty below LIMIT At Min PWM Duty below LIMIT Off/Min Bit 0 1 Table 15 PWM Output Below Limit Depending on Value of Off/Min Register 64-66h: Minimum PWM Duty Cycle Register Address 64h 65h 66h Read/ Write R/W R/W R/W Register Name Fan 1 PWM Minimum Fan 2 PWM Minimum Fan 3 PWM Minimum Bit 7 (MSB) 7 7 7 Bit 6 6 6 6 Bit 5 5 5 5 Bit 4 4 4 4 Bit 3 3 3 3 Bit 2 2 2 2 Bit 1 1 1 1 Bit 0 (LSB) 0 0 0 Default Value 80 80 80 Lock X X X This register specifies the minimum duty cycle that the PWM will output when the measured temperature reaches the Temperature LIMIT register setting. This register becomes Read-only when the Ready/Lock/Start/Override register Lock bit is set. Any further attempts to write to this register shall have no effect. Register Value Binary 0% ~25% ~50% (Default) ~75% 100% 0000 0100 1000 1100 1111 0000 0000 0000 0000 1111 Hex 00 40 80 C0 FF Minimum PWM % Table 16 Minimum PWM Duty Cycle Setting (c) Andigilog, Inc. 2006 - 30 www.andigilog.com October 2006 - 70A05007 aSC7611 Register 38-3Ah: Maximum PWM Duty Cycle Register Address 38h 39h 3Ah Read/ Write R/W R/W R/W Register Name Fan 1 Max Duty Cycle Fan 2 Max Duty Cycle Fan 3 Max Duty Cycle Bit 7 (MSB) 7 7 7 Bit 6 6 6 6 Bit 5 5 5 5 Bit 4 4 4 4 Bit 3 3 3 3 Bit 2 2 2 2 Bit 1 1 1 1 Bit 0 (LSB) 0 0 0 Default Value FF FF FF The Maximum PWM Duty registers store the maximum duty cycle that may be commanded at each PWM output under automatic fan control. This value is overridden to 100% when the assigned zone's temperature has exceeded the Absolute Maximum Temperature setting. When temperature falls below Absolute Maximum, PWM command will resume the linear ramp only after it has fallen by the Thermal Zone Hysteresis value (Registers 6D-6Eh). Values follow the representation in Table 10. Preliminary Specification - Subject to change without notice Preliminary Specification - Subject to change without notice Register 67-69h: Temperature Limit Register Address 67h 68h 69h Read/ Write R/W R/W R/W Register Name Zone1 Fan Temp Limit Zone2 Fan Temp Limit Zone 3 Fan Temp Limit Bit 7 (MSB) 7 7 7 Bit 6 6 6 6 Bit 5 5 5 5 Bit 4 4 4 4 Bit 3 3 3 3 Bit 2 2 2 2 Bit 1 1 1 1 Bit 0 (LSB) 0 0 0 Default Value 5A 5A 5A Lock X X X These are the temperature limits for the individual zones. When the current temperature equals this limit, the fan will be turned on if it is not already. When the temperature exceeds this limit, the fan speed will be increased according to the algorithm set forth in the Auto Fan Range, PWM Frequency register description, Default = 90C = 5Ah This register becomes read-only when the Ready/Lock/Start/Override register Lock bit is set. Any further attempts to write to this register shall have no effect. Temperature >127C +127C +125C +90C (default) +50C +25C 0C -50C -127C Fan Temp Limit (2's Complement) 0111 0111 0111 0101 0011 0001 0000 1100 1000 1111 1111 1101 1010 0010 1001 0000 1110 0001 Table 17 Fan Temperature Limit Register 8-Bit Two's Complement (c) Andigilog, Inc. 2006 - 31 www.andigilog.com October 2006 - 70A05007 aSC7611 Register 6A-6Ch: Temperature Limit Register Address 6Ah 6Bh 6Ch Read/ Write R/W R/W R/W Register Name Zone 1 Temp Absolute Limit Zone 2 Temp Absolute Limit Zone 3 Temp Absolute Limit Bit 7 (MSB) 7 7 7 Bit 6 6 6 6 Bit 5 5 5 5 Bit 4 4 4 4 Bit 3 3 3 3 Bit 2 2 2 2 Bit 1 1 1 1 Bit 0 (LSB) 0 0 0 Default Value 64 64 64 Lock X X X In the Auto Fan mode, if a zone exceeds the temperature set in the Absolute Temperature Limit register, all of the PWM outputs will increase its duty cycle to 100%. This is a safety feature that attempts to cool the system if there is a potentially catastrophic thermal event. If set to 80h (-128C), the feature is disabled. Default = 100 C = 64h. The PWM will remain at 100% until the assigned zone temperature falls below the Absolute Temp Limit for that zone by an amount equal to the hysteresis value for that zone. Preliminary Specification - Subject to change without notice Preliminary Specification - Subject to change without notice These registers become read-only when the Ready/Lock/Start/Override register Lock bit is set. Any further attempts to write to these registers shall have no effect. Temperature >127C +127C +125C +100C (default) +50C +25C 0C -50C -127C -128C (Disable) Absolute Limit (2's Complement) 0111 0111 0111 0110 0011 0001 0000 1100 1000 1000 1111 1111 1101 0100 0010 1001 0000 1110 0001 0000 Table 18 Absolute Temperature Limit Register 8-Bit Two's Complement Register 6D-6Eh: Thermal Zone Hysteresis Register Address 6Dh 6Eh Read/ Write R/W R/W Register Name Zone 1 and Zone 2 Hysteresis Zone 3 Hysteresis Bit 7 (MSB) H1-3 H3-3 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) H2-0 RES Default Value 44 40 Lock H1-2 H3-2 H1-1 H3-1 H1-0 H3-0 H2-3 RES H2-2 RES H2-1 RES X X If the temperature is above Fan Temp Limit, then drops below Fan Temp Limit, the following will occur: * The fan will remain on, at Fan PWM Minimum, until the temperature goes a certain amount below Fan Temp Limit. * The Hysteresis registers control this amount. See below table for details, all values from 0C to 15C are possible. This register becomes read-only when the Ready/Lock/Start/Override register Lock bit is set. Any further attempts to write to these registers shall have no effect. (c) Andigilog, Inc. 2006 - 32 www.andigilog.com October 2006 - 70A05007 aSC7611 Temperature 0C 1C 4C (default) 10C 15C Zone Hysteresis Hn-[3:0] 0000 0001 0100 1010 1111 Table 19 Zone Hysteresis Register Format Register 75h: Fan Spin-Up Mode Register Address Read/ Write R/W Register Name Fan SpinUp Mode Bit 7 (MSB) Tach4 Disable Bit 6 Tach3/4 Disable Bit 5 Tach2 Disable Bit 4 Tach1 Disable Bit 3 RES Bit 2 PWM3 SU Bit 1 PWM2 SU Bit 0 (LSB) PWM1 SU Default Value 00 Lock Preliminary Specification - Subject to change without notice Preliminary Specification - Subject to change without notice 75h X The PWM SU bit configures the PWM spin-up mode. If PWM SU is cleared the spin-up time will terminate after time programmed by the Fan Configuration register has elapsed. When set to 1, the spin-up time will terminate early if the TACH reading interpreted as RPM exceeds the Tach Minimum RPM value or after the time programmed by the Fan Configuration register has elapsed, which ever occurs first. Note that the magnitudes of the tach readings and the limits in the registers represent a time period that is inversely proportional to RPM. This register becomes Read-only when the Ready/Lock/Start/Override register Lock bit is set. Any further attempts to write to this register shall have no effect. Miscellaneous Registers Register 3Eh: Company ID Register Address 3Eh Read/ Write R Register Name Company ID Bit 7 (MSB) 7 Bit 6 6 Bit 5 5 Bit 4 4 Bit 3 3 Bit 2 2 Bit 1 1 Bit 0 (LSB) 0 Default Value 61 The company ID register contains the company identification number. For Andigilog this is 61h. This number is assigned by Intel and is a method for uniquely identifying the part manufacturer. This register is read-only - a write to this register has no effect. Register 3Fh: Version/Stepping Register Address 3Fh Read/ Write R Register Name Version/Stepping Bit 7 (MSB) VER3 Bit 6 VER2 Bit 5 VER1 Bit 4 VER0 Bit 3 STP3 Bit 2 STP2 Bit 1 STP1 Bit 0 (LSB) STP0 Default Value 69 The four least significant bits of the Version/Stepping register [3:0] contain the current stepping of the aSC7611 silicon. The four most significant bits [7:4] reflect the aSC7611 base device number when set to a value of 0110b. For the aSC7611, this register will read 01101001b (69h). The register is used by application software to identify which device in the hardware monitor family has been implemented in the given system. Based on this information, software can determine which registers to read from and write to. Further, application software may use the current stepping to implement work-around for bugs found in a specific silicon stepping. This register is read-only - a write to this register has no effect. Register 6Fh: Test Register Register Address 6Fh Read/ Write R/W Register Name Test Register Bit 7 (MSB) RES Bit 6 RES Bit 5 RES Bit 4 RES Bit 3 RES Bit 2 RES Bit 1 RES Bit 0 (LSB) XEN Default Value 00h Lock X (c) Andigilog, Inc. 2006 - 33 www.andigilog.com October 2006 - 70A05007 aSC7611 XOR Tree Test The aSC7611 incorporates a XOR tree test mode. When the test mode is enabled by setting the "XEN" bit high in the Test Register at address 6Fh via the SMBus, the part will enter XOR test mode. Since the test mode an XOR tree, the order of the signals in the tree is not important. SMBDAT and SMBCLK are not to be included in the test tree. This register becomes Read-Only when the Ready/Lock/Start/Override register Lock bit is set. Any further attempts to write to this registers shall have no effect. VID0 VID1 VID2 Preliminary Specification - Subject to change without notice Preliminary Specification - Subject to change without notice VID3 VID4 TACH1 TACH2 TACH3 TACH4 XTESTOUT PWM2 PWM3 Register 70-7Fh: Vendor Specific Registers These registers are for vendor specific features, including test registers. They will not default to a specific value on power up. (c) Andigilog, Inc. 2006 - 34 www.andigilog.com October 2006 - 70A05007 aSC7611 Applications Information Remote Diodes The aSC7611 is designed to work with a variety of remote sensors in the form of the substrate thermal diode of a CPU or graphics controller or a diode-connected transistor. Actual diodes are not suited for these measurements. There is some variation in the performance of these diodes, described in terms of its departure from the ideal diode equation. This factor is called diode nonideality, nf . The equation relating diode temperature to a change in thermal diode voltage with two driving currents is: Although the temperature error caused by non-ideality difference is directly proportional to the difference from 1.008, but a small difference in non-ideality results in a relatively large difference in temperature reading. For example, if there were a 1% tolerance in the non-Ideality of a diode it would result in a 2.7 degree difference (at 0C) in the result (0.01 x 273.15). This difference varies with temperature such that a fixed offset value may only be used over a very narrow range. Typical correction method required when measuring a wide range of temperature values is to scale the temperature reading in the host firmware. Preliminary Specification - Subject to change without notice Preliminary Specification - Subject to change without notice VBE where: KT = (nf ) ln( N ) q Part PentiumTM III (CPUID 68h) Pentium 4, 130nM Pentium 4, 90nM Pentium 4, 65nM Intel Pentium M AMD AthlonTM Model 6 AMD DuronTM Models 7 and 8 AMD Athlon Models 8 and 10 2N3904 nf Min 1.0057 1.001 nf Nom 1.008 1.002 1.011 1.009 nf Max 1.0125 1.003 Series Res nf = diode non-ideality factor, (nominal 1.009). -23 K = Boltzman's constant, (1.38 x 10 ). T = diode junction temperature in Kelvins. -19 q = electron charge (1.6 x 10 Coulombs). N = ratio of the two driving currents (16). The aSC7611 is designed and trimmed for an expected nf value of 1.009, based on the typical value for the Intel PentiumTM III and AMD AthlonTM. There is also a tolerance on the value provided. The values for other CPUs and the 2N3904 may have different nominal values and tolerances. Consult the CPU or GPU manufacturer's data sheet for the nf factor. Table 20 gives a representative sample of what one may expect in the range of non-ideality. The trend with CPUs is for a lower value with a larger spread. When thermal diode has a non-ideality factor other than 1.009 the difference in temperature reading at a particular temperature may be interpreted with the following equation: 1.009 Tactual = Treported n actual 3.64 3.33 4.52 1.0015 1.002 1.002 1.0000 1.003 1.0022 1.008 1.008 1.0037 1.0046 1.0029 1.016 1.016 1.0090 1.005 3.06 Table 20 Representative CPU Thermal Diode and Transistor Non-Ideality Factors CPU or ASIC Substrate Remote Diodes A substrate diode is a parasitic PNP transistor that has its collector tied to ground through the substrate and the base (Remote -) and emitter (Remote +) brought out to pins. Connection to these pins is shown in Figure 11. The non-ideality figures in Table 20 include the effects of any package resistance and represent the value seen from the CPU socket. The temperature indicated will need to be compensated for the departure from a non-ideality of 1.008. Remote + where: Treported = reported temperature in temperature register. Tactual = actual remote diode temperature. nactual = selected diode's non-ideality factor, nf . Temperatures are in Kelvins or C + 273.15. CPU Substrate aSC7611 Remote - This equation assumes that the series resistance of the remote diode is the same for each. This resistance is given in the data sheet for the CPU and may vary from 2.5 to 4.5. Figure 11 CPU Remote Diode Connection October 2006 - 70A05007 (c) Andigilog, Inc. 2006 - 35 www.andigilog.com aSC7611 Series Resistance Any external series resistance in the connections from the aSC7611 to the CPU pins should be accounted for in interpreting the results of a measurement. The impact of series resistance on the measured temperature is a result of measurement currents developing offset voltages that add to the diode voltage. This is relatively constant with temperature and may be corrected with a fixed value in the offset register. To determine the temperature impact of resistance is as follows: TR = RS x I D / TV or, TR = RS x 90A = RS x 0.391C / 230V / C transistor's die temperature is usually not the temperature of interest and care must be taken to minimize the thermal resistance and physical distance between that temperature and the remote diode. The offset and response time will need to be characterized by the user. Board Layout Considerations The distance between the remote sensor and the aSC7611 should be minimized. All wiring should be defended from high frequency noise sources and a balanced differential layout maintained on Remote + and Remote -. Any noise, both common-mode and differential, induced in the remote diode interconnect may result in an offset in the temperature reported. Circuit board layout should follow the recommendation of Figure 13. Basically, use 10-mil lines and spaces with grounds on each side of the differential pair. Choose the ground plane closest to the CPU when using the CPU's remote diode. 10 mil Line 10 mil Space GND Remote + Remote GND Preliminary Specification - Subject to change without notice Preliminary Specification - Subject to change without notice where: TR = difference in the temperature reading from actual. RS = total series resistance of interconnect (both leads). I D = difference in the two diode current levels (90A). TV = scale of temperature vs. VBE (230V/C). For example, a total series resistance of 10 would give an offset of +3.9C. Discrete Remote Diodes When sensing temperatures other than the CPU or GPU substrate, an NPN or PNP transistor may be used. Most commonly used are the 2N3904 and 2N3906. These have characteristics similar to the CPU substrate diode with non-ideality around 1.0046. They are connected with base to collector shorted as shown in Figure 12. While it is important to minimize the distance to the remote diode to reduce high-frequency noise pickup, they may be located many feet away with proper shielding. Shielded, twisted-pair cable is recommended, with the shield connected only at the aSC7611 end as close as possible to the ground pin of the device. Remote + Figure 13 Recommended Remote Diode Circuit Board Interconnect Noise filtering is accomplished by using a bypass capacitor placed as close as possible to the two pairs of aSC7611 Remote + and Remote - pins. A 1.0nF ceramic capacitor is recommended, but up to 3.3nF may be used. Additional filtering takes place within the aSC7611. It is recommended that the following guidelines be used to minimize noise and achieve highest accuracy: 1. Place a 0.1F bypass capacitor to digital ground as close as possible to the power pin of the aSC7611. Match the trace routing of the Remote + and Remote - leads and use a 1.0nF filter capacitor close to the aSC7611. Use ground runs along side the pair to minimize differential coupling as in Figure 13. Place the aSC7611 as close to the CPU or GPU remote diode leads as possible to minimize noise and series resistance. Avoid running diode connections close to or in parallel with high-speed busses or 12V, staying at least 2cm away. Avoid running diode connections close to on-board switching power supply inductors. October 2006 - 70A05007 2. 2N3906 aSC7611 Remote Remote + 2N3904 aSC7611 Remote - 3. Figure 12 Discrete Remote Diode Connection As with the CPU substrate diode, the temperature reported will be subject to the same errors due to nonideality variation and series resistance. However, the (c) Andigilog, Inc. 2006 4. 5. - 36 www.andigilog.com aSC7611 6. PC board leakage should be minimized by maintaining minimum trace spacing and covering traces over their full length with solder mask. BIOS code. After optimization, the settings may then be programmed into the BIOS. Features: * Interactive GUI for setting limits and operational configuration * aSC7512 and aSC7611 Automatic Fan Control * Powered and operated from the USB port * Support for reading or writing to any register * User-defined, time-stamped logging of any registers, saved in spreadsheet-compatible format * Graphical readouts: * Temperature and alarms * Fan RPM * Automatic fan control state * Voltage * Selectable on-board 2N3904 or wired remote diode * Headers for 2-, 3- and 4-wire fans with PWM drive for aSC7512 * Headers for up to 3 4-wire fans for aSC7611 * Saving and recalling of full register set configurations * LED indicators of alarm pin states * Optional use of external 12V fan power for higher current fans * Optional connection to off-board SMBus clients Thermal Considerations The temperature of the aSC7611 will be close to that of the PC board on which it is mounted. Conduction through the leads is the primary path for heat flow. The reported local sensor is very close to the circuit board temperature and typically between the board and ambient. In order to measure PC board temperature in an area of interest, such as the area around the CPU where voltage regulator components generate significant heat, a remote diode-connected transistor should be used. A surfacemount SOT-23 or SOT-223 is recommended. The small size is advantageous in minimizing response time because of its low thermal mass, but at the same time it has low surface area and a high thermal resistance to ambient air. A compromise must be achieved between minimizing thermal mass and increasing the surface area to lower the junction-to-ambient thermal resistance. In order to sense temperature of air-flows near boardmounted heat sources, such as memory modules, the sensor should be mounted above the PC board. A TO-92 packaged transistor is recommended. The power consumption of the aSC7611 is relatively low and should have little self-heating effect on the local sensor reading. At the highest measurement rate the dissipation is less than 2mW, resulting in only a few tenths of a degree rise. Preliminary Specification - Subject to change without notice Preliminary Specification - Subject to change without notice Application Diagram The aSC7611 may be easily adapted to two-, three- or 4wire fans for precise, wider-range fan speed control when compared to variable DC drive. Up to four fans may be controlled. Fans 1 and 2 are independent. Fan 3 is independent and may be tied to fan 4 for speed control. Separate tachometer readings may be reported for all four. Application diagram in Figure 14 shows connections to four 4-wire fans. External FETs may be added to the PWM output to drive 3-wire fans. Evaluation Board The Andigilog SMBus EVB provides a platform for evaluation of the operational characteristics of the aSC7511, aSC7512 and aSC7611. The board features a graphical user interface (GUI) to control and monitor all activities and readings of these parts. The provided software will run on a Windows XPTM-based desktop or laptop PC with a USB port. In addition to being a self-contained fan speed control demonstration, it may be connected into an operating PC's fan and CPU diode to evaluate various settings under real operating conditions without the need to adjust (c) Andigilog, Inc. 2006 - 37 www.andigilog.com October 2006 - 70A05007 aSC7611 12V 10K 15K REMOTE 1+ CPU Substrate 1nF REMOTE 1- TACH 1 PWM 1 7.5K 0.01F 12V 2N3904 1nF REMOTE 2 + REMOTE 2 - Preliminary Specification - Subject to change without notice 10K 15K Preliminary Specification - Subject to change without notice TACH 2 PWM 2 7.5K 12V 10K 15K 0.01F VCCP 2.5V 5V 12V 3.3V VCCP 2.5V 5V 12V 3.3V GND TACH 3 PWM 3 7.5K 0.1F 100pF aSC7611 CPU Voltage IDs SMBus VID0 VID1 VID2 VID3 VID4 SMBDAT SMBCLK 0.01F 12V 10K 15K TACH 4 7.5K 0.01F Figure 14 Application Diagram (c) Andigilog, Inc. 2006 - 38 www.andigilog.com October 2006 - 70A05007 aSC7611 Physical Dimensions inches unless otherwise noted 24-Lead Molded QSOP Package D X 0.010 E1 E 2 Pin 1 L e b GAUGE PLANE SEATING PLANE Preliminary Specification - Subject to change without notice Preliminary Specification - Subject to change without notice DETAIL "A" 0.015 0.004 x 45 A1 1 A DETAIL "A" C Notes: 1. 2. 3. 4. 5. Pb-Free Co-planarity is 0 to 0.004" MAX Package surface finish - Matte (VDI #24~27) All dimensions exclude mold flash The lead width, B, to be determined at 0.0075" from the lead tip Symbol A A1 B D E1 E E C L X 1 2 MIN 0.054 0.004 0.008 0.337 0.150 0.229 0.0075 0.016 0 MAX 0.068 0.0098 0.012 0.344 0.157 0.244 0.0098 0.034 8 7 BSC 0.025 BSC 0.0325 REF (c) Andigilog, Inc. 2006 - 39 www.andigilog.com October 2006 - 70A05007 aSC7611 Data Sheet Classifications Preliminary Specification This classification is shown on the heading of each page of a specification for products that are either under development (design and qualification), or in the formative planning stages. Andigilog reserves the right to change or discontinue these products without notice. New Release Specification This classification is shown on the heading of the first page only of a specification for products that are either under the later stages of development (characterization and qualification), or in the early weeks of release to production. Andigilog reserves the right to change the specification and information for these products without notice. Preliminary Specification - Subject to change without notice Preliminary Specification - Subject to change without notice Fully Released Specification Fully released datasheets do not contain any classification in the first page header. These documents contain specification on products that are in full production. Andigilog will not change any guaranteed limits without written notice to the customers. Obsolete datasheets that were written prior to January 1, 2001 without any header classification information should be considered as obsolete and non-active specifications, or in the best case as Preliminary Specifications. PentiumTM is a trademark of Intel Corporation AthlonTM and DuronTM are trademarks of AMD Corporation Windows XPTM is a trademark of Microsoft Corporation LIFE SUPPORT POLICY ANDIGILOG'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF ANDIGILOG, INC. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Andigilog, Inc. 8380 S. Kyrene Rd., Suite 101 Tempe, Arizona 85284 Tel: (480) 940-6200 Fax: (480) 940-4255 (c) Andigilog, Inc. 2006 - 40 www.andigilog.com October 2006 - 70A05007 |
Price & Availability of ASC7611QS24
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |